1 tm file number 3402.3 hs-26c32rh radiation hardened quad differential line receiver the intersil hs-26c32rh is a differential line receiver designed for digital data transmission over balanced lines and meets the requirements of eia standard rs-422. radiation hardened cmos processing assures low power consumption, high speed, and reliable operation in the most severe radiation environments. the hs-26c32rh has an input sensitivity typically of 200mv over the common mode input voltage range of 7v. the receivers are also equipped with input fail safe circuitry, which causes the outputs to go to a logic ? when the inputs are open. enable and disable functions are common to all four receivers. speci?ations for rad hard qml devices are controlled by the defense supply center in columbus (dscc). the smd numbers listed here must be used when ordering. detailed electrical speci?ations for these devices are contained in smd 5962-95689. a ?ot-link?is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp logic diagram features electrically screened to smd # 5962-95689 qml quali?d per mil-prf-38535 requirements 1.2 micron radiation hardened cmos - total dose. . . . . . . . . . . . . . . . . . . . . 300 krad(si) (max) latchup free eia rs-422 compatible inputs cmos compatible outputs input fail safe circuitry high impedance inputs when disabled or powered down low power dissipation 138mw standby (max) single 5v supply full -55 o c to 125 o c military temperature range pinouts hs1-26c32rh 16 lead ceramic sidebraze dip mil-std-1835: cdip2-t16 top view hs9-26c32rh 16 lead flatpack mil-std-1835: cdfp4-f16 top view ordering information ordering no. internal mkt. no. temp. range ( o c) 5962f9568901qec hs1-26c32rh-8 -55 to 125 5962f9568901qxc hs9-26c32rh-8 -55 to 125 5962f9568901v9a HS0-26C32RH-Q 25 5962f9568901vec hs1-26c32rh-q -55 to 125 5962f9568901vxc hs9-26c32rh-q -55 to 125 hs1-26c32rh/proto hs1-26c32rh/proto -55 to 125 hs9-26c32rh/proto hs9-26c32rh/proto -55 to 125 enable enable aout bout cout din dout din cin cin bin bin ain ain +- +- +- +- 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 ain ain aout enable cout cin gnd cin vdd bin bout enable dout din din bin ain ain aout enable cout cin cin gnd 2 3 4 5 6 7 8 116 15 14 13 12 11 10 9 vdd bin bin bout enable dout din din data sheet august 2000 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright ?intersil corporation 2000
2 propagation delay timing diagram three-state low timing diagram three-state low load circuit propagation delay load circuit three-state high timing diagrams three-state high load circuit three-state low voltage levels parameter hs-26c32rh units v dd 4.50 v v ih 4.50 v v s 2.25 v v t 50 % v w v ol + 0.5 v gnd 0 v input output -v in +v in = 0v v oh v ol 0v -2.5v +2.5v v s = 50% t plh t phl v s input v ih v ss t pzl t plz output v oz v ol v t v w dut test c l r l point c l = 50pf r l = 1000 ? v dd three-state high voltage levels parameter hs-26c32rh units v dd 4.50 v v ih 4.50 v v s 2.25 v v t 50 % v w v oh - 0.5 v gnd 0 v dut test c l r l point c l = 50pf r l = 1000 ? v s input t pzh t phz output v oh v oz v t v w v ih v ss dut test c l r l point c l = 50pf r l = 1000 ? hs-26c32rh
3 die characteristics die dimensions: 84 mils x 130 mils (2140 m x 3290 m) interface materials: glassivation: type: sio 2 thickness: 10k ? 1k ? top metallization: m1: mo/tiw thickness: 5800 ? m2: al/si/cu thickness: 5800 ? worst case current density: <2.0 x 10 5 a/cm 2 bond pad size: 110 m x 100 m metallization mask layout hs-26c32rh ain v dd bin ain (2) a out (3) enab (4) c out (5) c in (6) (8) (9) (14) b in (13) b out (12) enab (11) d out (10) d in (1) (16) (15) (7) cin gnd din hs-26c32rh
4 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil ltd. 8f-2, 96, sec. 1, chien-kuo north, taipei, taiwan 104 republic of china tel: 886-2-2515-8508 fax: 886-2-2515-8369 hs-26c32rh
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